SAMA5D41_14 Datasheet, PDF (99/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

14.5.9 L2CC Event Counter 0 Configuration Register
Name:
L2CC_ECFGR0
Address: 0x00A00208
Access:
Read-write
31
30
29
28
27
26
–
–
–
–
–
–
23
22
21
20
19
18
–
–
–
–
–
–
15
14
13
12
11
10
–
–
–
–
–
–
7
6
5
4
3
2
–
–
ESRC
• EIGEN: Event Counter Interrupt Generation
Value
0x0
0x1
0x2
0x3
Name
INT_DIS
INT_EN_INCR
INT_EN_OVER
INT_GEN_DIS
• ESRC: Event Counter Source
Description
Disables (default)
Enables with Increment condition
Enables with Overflow condition
Disables Interrupt generation
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
Name
CNT_DIS
SRC_CO
SRC_DRHIT
SRC_DRREQ
SRC_DWHIT
SRC_DWREQ
SRC_DWTREQ
SRC_IRHIT
SRC_IRREQ
SRC_WA
SRC_IPFALLOC
SRC_EPFHIT
SRC_EPFALLOC
SRC_SRRCVD
SRC_SRCONF
SRC_EPFRCVD
Description
Counter Disabled
Source is CO
Source is DRHIT
Source is DRREQ
Source is DWHIT
Source is DWREQ
Source is DWTREQ
Source is IRHIT
Source is IRREQ
Source is WA
Source is IPFALLOC
Source is EPFHIT
Source is EPFALLOC
Source is SRRCVD
Source is SRCONF
Source is EPFRCVD
25
24
–
–
17
16
–
–
9
8
–
–
1
0
EIGEN
SAMA5D4 Series [DATASHEET]
99
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14