SAMA5D41_14 Datasheet, PDF (1555/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

48.7.4 ADC Channel Enable Register
Name:
Address:
Access:
ADC_CHER
0xFC034010
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
CH4
CH3
CH2
CH1
CH0
This register can only be written if the WPEN bit is cleared in the “ADC Write Protection Mode Register” .
• CHx: Channel x Enable
0: No effect.
1: Enables the corresponding channel.
Note: If USEQ = 1 in the ADC_MR, CHx corresponds to the xth channel of the sequence described in ADC_SEQR1.
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
1555