ATMEGA8_14 Datasheet, PDF (54/331 Pages) ATMEL Corporation – High-performance, Low-power Atmel

ATmega8(L)
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows t_pd,max and t_pd,min, a single signal transition on the pin will be delayed
between ½ and 1-½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in Figure 24. The out instruction sets the “SYNC LATCH” signal at the positive edge of the
clock. In this case, the delay t_pd through the synchronizer is 1 system clock period.
Figure 24. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
r16
0xFF
INSTRUCTIONS
out PORTx, r16
nop
in r17, PINx
SYNC LATCH
PINxn
r17
0x00
t _pd
0xFF
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