ATMEGA8_14 Datasheet, PDF (230/331 Pages) ATMEL Corporation – High-performance, Low-power Atmel

ATmega8(L)
Serial
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Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in Table 96, the pin mapping for SPI
programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface.
Serial
Programming Pin
Mapping
Table 96. Pin Mapping Serial Programming
Symbol
Pins
I/O
MOSI
PB3
I
MISO
PB4
O
SCK
PB5
I
Figure 112. Serial Programming and Verify⁽¹⁾
MOSI
MISO
SCK
PB3
PB4
PB5
XTAL1
Description
Serial data in
Serial data out
Serial clock
+2.7V - 5.5V
VCC
+2.7V - 5.5V ⁽²⁾
AVCC
RESET
GND
Notes: 1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin
2. V_CC - 0.3 < AV_CC < V_CC + 0.3, however, AV_CC should always be within 2.7V - 5.5V
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the Serial Clock (SCK) input are defined as follows:
Low:> 2 CPU clock cycles for f_ck <12MHz, 3 CPU clock cycles for f_ck >=12MHz
High:> 2 CPU clock cycles for f_ck <12MHz, 3 CPU clock cycles for f_ck >=12MHz
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