ATMEGA8_14 Datasheet, PDF (132/331 Pages) ATMEL Corporation – High-performance, Low-power Atmel

ATmega8(L)
Double Speed
Operation (U2X)
External Clock
Synchronous Clock
Operation
Table 52. Equations for Calculating Baud Rate Register Setting
Operating Mode
Equation for Calculating
Baud Rate⁽¹⁾
Equation for Calculating
UBRR Value
Asynchronous Normal mode
(U2X = 0)
Asynchronous Double Speed
Mode (U2X = 1)
Synchronous Master Mode
BAUD = -₁---₆----_--_U----^f-_B-^O---_R-^S---^C_R------+-----₁----_
BAUD = -₈---_---_U----_B-^f--^O--_R--^S--_R-^C-----+----₁----_-
BAUD = -₂---_---_U----_B-^f--^O--_R--^S--_R-^C-----+----₁----_-
UBRR = ₁----₆---^fB--^O---_A^S---^C-_U----_D--- – 1
UBRR = ₈----_B-^f--^O-_A---^S-_U-^C----_D--- – 1
UBRR = ₂----_B-^f--^O-_A---^S-_U-^C----_D--- – 1
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD Baud rate (in bits per second, bps)
fOSC System Oscillator clock frequency
UBRR Contents of the UBRRH and UBRRL Registers (0 - 4095)
Some examples of UBRR values for some system clock frequencies are found in Table 60 on
page 153.
The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect
for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
External clocking is used by the Synchronous Slave modes of operation. The description in this
section refers to Figure 62 on page 131 for details.
External clock input from the XCK pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
duces a two CPU clock period delay and therefore the maximum external XCK clock frequency
is limited by the following equation:
f_XCK

-^f-^O----^S---^C--
4
Note that f_osc depends on the stability of the system clock source. It is therefore recommended to
add some margin to avoid possible loss of data due to frequency variations.
When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxD) is sampled at the
opposite XCK clock edge of the edge the data output (TxD) is changed.
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