ATMEGA8_14 Datasheet, PDF (160/331 Pages) ATMEL Corporation – High-performance, Low-power Atmel

ATmega8(L)
Data Packet Format
All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and
an acknowledge bit. During a data transfer, the Master generates the clock and the START and
STOP conditions, while the Receiver is responsible for acknowledging the reception. An
Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL
cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has
received the last byte, or for some reason cannot receive any more bytes, it should inform the
Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.
Figure 72. Data Packet Format
Aggregate
SDA
Data MSB
SDA from
Transmitter
SDA from
Receiver
SCL from
Master
SLA+R/W
1
2
Data LSB ACK
7
8
9
Data Byte
STOP, REPEATED
START or Next
Data Byte
Combining Address
and Data Packets into
a Transmission
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets
and a STOP condition. An empty message, consisting of a START followed by a STOP condi-
tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement
handshaking between the Master and the Slave. The Slave can extend the SCL low period by
pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the
Slave, or the Slave needs extra time for processing between the data transmissions. The Slave
extending the SCL low period will not affect the SCL high period, which is determined by the
Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the
SCL duty cycle.
Figure 73 shows a typical data transmission. Note that several data bytes can be transmitted
between the SLA+R/W and the STOP condition, depending on the software protocol imple-
mented by the application software.
Figure 73. Typical Data Transmission
SDA
Addr MSB
Addr LSB R/W ACK
SCL
START
1
2
7
8
9
SLA+R/W
Data MSB
Data LSB ACK
1
2
7
8
9
Data Byte
STOP
2486AA–AVR–02/2013
160