ATMEGA8_14 Datasheet, PDF (239/331 Pages) ATMEL Corporation – High-performance, Low-power Atmel

ATmega8(L)
5. This requirement applies to all ATmega8 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial
Bus need only obey the general f_SCL requirement
6. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/f_SCL - 2/f_CK), thus f_CK must be greater than
6MHz for the low time requirement to be strictly met at f_SCL = 100kHz
7. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/f_SCL - 2/f_CK), thus the low time requirement
will not be strictly met for f_SCL > 308kHz when f_CK = 8MHz. Still, ATmega8 devices connected to the bus may communicate at
full speed (400kHz) with other ATmega8 devices, as well as any other device with a proper t_LOW acceptance margin
Figure 115. Two-wire Serial Bus Timing
t_of
t_HIGH
SCL
SDA
t_SU;STA
t_LOW
t_HD;STA
t_LOW
t_HD;DAT
t_SU;DAT
t_r
t_SU;STO
t_BUF
SPI Timing
Characteristics
See Figure 116 on page 240 and Figure 117 on page 240 for details.
Table 102. SPI Timing Parameters
Description
Mode
1
SCK period
Master
2
SCK high/low
3
Rise/Fall time
4
Setup
5
Hold
6
Out to SCK
7
SCK to out
8
SCK to out high
9
SS low to out
10
SCK period
11
SCK high/low⁽¹⁾
12
Rise/Fall time
13
Setup
14
Hold
15
SCK to out
16
SCK to SS high
17
SS high to tri-state
18
SS low to SCK
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Salve
Min
4 • t_ck
2 • t_ck
10
10
20
2 • t_ck
Typ
Max
See Table 50 on
page 126
50% duty cycle
3.6
10
10
0.5 • t_SCK
10
10
15
ns
1600
15
10
Note:
1. In SPI Programming mode the minimum SCK high/low period is:
- 2t_CLCL for f_CK < 12MHz
- 3t_CLCL for f_CK > 12MHz
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