ATMEGA8_14 Datasheet, PDF (44/331 Pages) ATMEL Corporation – High-performance, Low-power Atmel

ATmega8(L)
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit
has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written
to WDE even though it is set to one before the disable operation starts
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods
are shown in Table 17.
Table 17. Watchdog Timer Prescale Select
WDP2
0
0
0
0
1
1
1
1
WDP1
0
0
1
1
0
0
1
1
WDP0
0
1
0
1
0
1
0
1
Number of WDT
Oscillator Cycles
16K (16,384)
32K (32,768)
64K (65,536)
128K (131,072)
256K (262,144)
512K (524,288)
1,024K (1,048,576)
2,048K (2,097,152)
Typical Time-out
at V_CC = 3.0V
17.1ms
34.3ms
68.5ms
0.14s
0.27s
0.55s
1.1s
2.2s
Typical Time-out
at V_CC = 5.0V
16.3ms
32.5ms
65ms
0.13s
0.26s
0.52s
1.0s
2.1s
The following code example shows one assembly and one C function for turning off the WDT.
The example assumes that interrupts are controlled (for example, by disabling interrupts glob-
ally) so that no interrupts will occur during execution of these functions.
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