ATMEGA8_14 Datasheet, PDF (17/331 Pages) ATMEL Corporation – High-performance, Low-power Atmel

ATmega8(L)
AVR ATmega8
Memories
This section describes the different memories in the Atmel^®AVR^® ATmega8. The AVR architec-
ture has two main memory spaces, the Data memory and the Program Memory space. In
addition, the ATmega8 features an EEPROM Memory for data storage. All three memory spaces
are linear and regular.
In-System
Reprogrammable
Flash Program
Memory
The ATmega8 contains 8Kbytes On-chip In-System Reprogrammable Flash memory for pro-
gram storage. Since all AVR instructions are 16-bits or 32-bits wide, the Flash is organized as
4K × 16 bits. For software security, the Flash Program memory space is divided into two sec-
tions, Boot Program section and Application Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega8 Pro-
gram Counter (PC) is 12 bits wide, thus addressing the 4K Program memory locations. The
operation of Boot Program section and associated Boot Lock Bits for software protection are
described in detail in “Boot Loader Support – Read-While-Write Self-Programming” on page
202. “Memory Programming” on page 215 contains a detailed description on Flash Program-
ming in SPI- or Parallel Programming mode.
Constant tables can be allocated within the entire Program memory address space (see the
LPM – Load Program memory instruction description).
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-
ing” on page 13.
Figure 7. Program Memory Map
$000
Application Flash Section
2486AA–AVR–02/2013
Boot Flash Section
$FFF
17