ATMEGA8_14 Datasheet, PDF (129/331 Pages) ATMEL Corporation – High-performance, Low-power Atmel

USART
Overview
ATmega8(L)
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly-flexible serial communication device. The main features are:
• Full Duplex Operation (Independent Serial Receive and Transmit Registers)
• Asynchronous or Synchronous Operation
• Master or Slave Clocked Synchronous Operation
• High Resolution Baud Rate Generator
• Supports Serial Frames with 5, 6, 7, 8, or 9 Databits and 1 or 2 Stop Bits
• Odd or Even Parity Generation and Parity Check Supported by Hardware
• Data OverRun Detection
• Framing Error Detection
• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
• Multi-processor Communication Mode
• Double Speed Asynchronous Communication Mode
A simplified block diagram of the USART Transmitter is shown in Figure 61. CPU accessible I/O
Registers and I/O pins are shown in bold.
Figure 61. USART Block Diagram⁽¹⁾
UBRR[H:L]
Clock Generator
OSC
BAUD RATE GENERATOR
SYNC LOGIC
UDR (Transmit)
TRANSMIT SHIFT REGISTER
PARITY
GENERATOR
RECEIVE SHIFT REGISTER
UDR (Receive)
CLOCK
RECOVERY
DATA
RECOVERY
PARITY
CHECKER
PIN
CONTROL
XCK
Transmitter
TX
CONTROL
PIN
CONTROL
TxD
Receiver
RX
CONTROL
PIN
CONTROL
RxD
UCSRA
UCSRB
UCSRC
2486AA–AVR–02/2013
Note: 1. Refer to “Pin Configurations” on page 2, Table 30 on page 64, and Table 29 on page 64 for
USART pin placement
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