NPE405H Datasheet, PDF (68/70 Pages) Applied Micro Circuits Corporation – PowerNP NPe405H Embedded Processor

NPe405H – PowerNP NPe405H Embedded Processor
Revision 1.01 – April 18, 2007
Data Sheet
INITIALIZATION
The following describes the method by which initial chip settings are established when a system reset occurs.
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable default initial con-
ditions prior to NPe405H start-up. The actual capture instant is the nearest SysClk edge before the deassertion of
reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the
desired default conditions. The recommended pull-up is 3kΩ to +3.3V or 10kΩ to +5 V, the recommended pull-
down is 1kΩ to GND.These pins are used for strap functions only during reset. They are used for other signals dur-
ing normal operation. The following table lists the strapping pins along with their functions and strapping options.
STRAPPING PIN ASSIGNMENTS
Table 17. Strapping Pin Assignments
Function
SEPROMPresent –
Serial EEPROM connection to the IIC interface
Option
Not connected
Connected
When SEPROMPresent = 1, these pins set the high-
order two bits of the EEPROM base address.
When SEPROMPresent = 0, these pins indicated
the width of the boot ROM.
High order EEPROM base address bits
8 bits
16 bits
32 bits
reserved
Ball Strapping
AJ33
(UART1_Tx)
0
1
H01
(HoldAck)
H02
(ExtAck)
x
x
0
0
0
1
1
0
1
1
EEPROM
During reset, configuration values other than those obtained from the strapping pins can be read from a serial
EEPROM connected to the IIC port. The association of bits in the EEPROM with the configuration values and their
default values are covered in detail in the PowerNP NPe405H Network Processor User’s Manual.
Caution: If SEPROMPresent is strapped to 1, and the EEPROM is not connected or is defective, the NPe405H
will not boot up.
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