NPE405H Datasheet, PDF (48/70 Pages) Applied Micro Circuits Corporation – PowerNP NPe405H Embedded Processor

NPe405H – PowerNP NPe405H Embedded Processor
Revision 1.01 – April 18, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 6 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.
Signal Name
Description
I/O
Type
[DMAReq0:3]
DMA request. Used by peripheral slaves to request a data
transfer. Following a system reset, the default mode of the
signals is active-low. They may be programmed to active-high
I
using the DMA0_POL register.
5V tolerant
3.3V LVTTL
[DMAAck0:3]
DMA acknowledge. Used to indicate to peripherals that data
transfer is complete. Following a system reset, the default
mode of the signals is active-low. They may be programmed
O
to active-high using the DMA0_POL register.
5V tolerant
3.3V LVTTL
[EOT0:3/TC0:3]
End Of Transfer/Terminal Count. Indication by peripherals
that all data has been transferred, or by DMA controller that
programmed amount of data has been transferred. Following
a system reset, the default mode of the signals is active-low.
I/O
They may be programmed to active-high using the
DMA0_POL register.
5V tolerant
3.3V LVTTL
Notes
1
1
48 DS2011
AMCC Proprietary