NPE405H Datasheet, PDF (46/70 Pages) Applied Micro Circuits Corporation – PowerNP NPe405H Embedded Processor

NPe405H – PowerNP NPe405H Embedded Processor
Revision 1.01 – April 18, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 4 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.
Signal Name
Description
I/O
Type
PHY0RxDV[PHY0CrS1DV]
Receive Data Valid. Data on the Data Bus is valid when this
signal is activated. Deassertion of this signal indicates end of
the frame reception (MII 0).
I
or
Carrier sense data valid ([RMII 1])
5V tolerant
3.3V LVTTL
PHY0RxErr[PHY0Rx0Er]
Receive Error. This signal comes from the PHY and is
synchronous with PHY0RxClk (MII 0 [RMII 0]).
I
5V tolerant
3.3V LVTTL
PHY0TxClk[PHY0RefClk]
Transmit medium clock. This signal is generated the PHY
([MII 0]).
or
Reference Clock [RMII and SMII].
I
5V tolerant
3.3V LVTTL
[PHY1Col][PHY1Rx3Er]
Collision [receive error] signal from the PHY. This is an
asynchronous signal ([MII 1]).
or
Receive Error. This signal comes from the PHY and is
synchronous with PHY1RxClk ([RMII 3]).
I
5V tolerant
3.3V LVTTL
[PHY1CrS][PHY1CrS2DV]
Carrier Sense signal from the PHY. This is an asynchronous
signal ([MII 1]).
or
I
5V tolerant
3.3V LVTTL
Carrier Sense Data Valid ([RMII 2]).
[PHY1RxClk]
Receiver medium clock. This signal is generated by the PHY
([MII 1]).
I
5V tolerant
3.3V LVTTL
[PHY1RxDV][PHY1CrS3DV]
Receive Data Valid ([MII 1]).
or
Carrier Sense Data Valid ([RMII 3]).
i
5V tolerant
3.3V LVTTL
[PHY1RxErr][PHY1Rx2Er]
Receive Error. This signal comes from the PHY and is
synchronous with PHY1RxClk ([MII 1][RMII 2]).
I
5V tolerant
3.3V LVTTL
[PHY1TxClk]
Transmit medium clock. This signal is generated the PHY
([MII 1]).
I
5V tolerant
3.3V LVTTL
SDRAM Interface
MemAddr00:31
Memory Data bus
Notes:
1. MemAddr00 is the most significant bit (msb).
2. MemData31 is the least significant bit (lsb).
I/O 3.3V LVTTL
MemAddr12:00
Memory Address bus.
Notes:
1. MemAddr12 is the most significant bit (msb).
2. MemAddr00 is the least significant bit (lsb).
O
3.3V LVTTL
BA1:0
Bank Address supporting up to 4 internal banks
O
3.3V LVTTL
RAS
Row Address Strobe.
O
3.3V LVTTL
CAS
Column Address Strobe.
O
3.3V LVTTL
DQM0:3
DQM for byte lane 0 (MemAddr00:7),
1 (MemAddr08:15),
2 (MemData16:23), and
3 (MemData24:31)
O
3.3V LVTTL
Notes
1, 5
1, 5
1, 4
1, 5
1, 4
1, 4
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