NPE405H Datasheet, PDF (64/70 Pages) Applied Micro Circuits Corporation – PowerNP NPe405H Embedded Processor

NPe405H – PowerNP NPe405H Embedded Processor
Revision 1.01 – April 18, 2007
Data Sheet
Table 15. I/O Specifications—133 and 200MHz (Sheet 3 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM. Output times in table are in cycle 1.
3. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load.
4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS
model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that
the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns)
Signal
Setup Time Hold Time
(T_IS min) (T_IH min)
SDRAM Interface
BA1:0
n/a
n/a
BankSel3:0
n/a
n/a
CAS
n/a
n/a
ClkEn0:1
n/a
n/a
DQM0:3
n/a
n/a
DQMCB
n/a
n/a
ECC0:7
2.7
1.0
MemAddr12:00
n/a
n/a
MemData00:31
2.8
1.0
RAS
n/a
n/a
WE
n/a
n/a
External Slave Peripheral Bus Interface
[DMAReq0:3]
[4.7]
[0.0]
[DMAAck0:3]
n/a
n/a
[EOT0:3/TC0:3]
[4.5]
[0.0]
PerAddr04:31
3.0
1.0
PerBLast
4.2
0.0
PerCS0
n/a
n/a
[PerCS1:7]
n/a
n/a
PerData00:31
5.7
1.0
PerOE
n/a
n/a
PerPar0:3
3.4
0.0
PerR/W
4.5
0.0
PerReady
7.6
0.0
PerWBE0:3
3.0
0.0
PerClk
n/a
n/a
PerErr
2.9
0.0
External Master Peripheral Bus Interface
BusReq
n/a
n/a
ExtAck
n/a
n/a
ExtReq
4.5
0.0
ExtReset
n/a
n/a
HoldAck
n/a
n/a
HoldPri
2.9
0.0
HoldReq
4.0
0.0
IIC EEPROM Controller
IECSCL
aysnc
aysnc
IECSDA
aysnc
aysnc
Output (ns)
Valid Delay Hold Time
(T_OV max) (T_OH min)
7.1
1.1
5.2
0.5
6.8
1.0
4.5
0.5
5.3
0.5
5.3
0.5
5.2
0.5
7.0
1.0
5.2
0.5
6.7
0.9
5.5
1.5
n/a
n/a
[8.5]
[1.0]
[8.6]
[1.0]
8.5
1.0
7.1
1.2
8.7
1.0
[8.7]
[1.0]
9.5
1.3
7.5
1.3
8.9
1.1
7.5
1.2
n/a
n/a
7.7
1.3
-0.6
-0.7
n/a
n/a
6.8
1.2
6.9
1.2
n/a
n/a
8.0
0.0
7.3
1.4
n/a
n/a
n/a
n/a
aysnc
aysnc
aysnc
aysnc
Output Current (mA)
I/O H
I/O L
(maximum) (minimum)
19
12
19
12
19
12
40
25
19
12
19
12
19
12
19
12
19
12
19
12
19
12
n/a
n/a
12
8
12
8
17
11
12
8
12
8
12
8
17
11
12
8
17
11
12
8
n/a
n/a
12
8
17
11
n/a
n/a
12
8
12
8
n/a
n/a
19
12
12
8
n/a
n/a
n/a
n/a
17
11
17
11
Clock
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PLB Clk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
Notes
2, 3
3
2, 3
3
3
3
3
2, 3
3
2, 3
2, 3
5
64 DS2011
AMCC Proprietary