NPE405H Datasheet, PDF (51/70 Pages) Applied Micro Circuits Corporation – PowerNP NPe405H Embedded Processor

NPe405H – PowerNP NPe405H Embedded Processor
Revision 1.01 – April 18, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 9 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.
Signal Name
Description
I/O
Type
System Interface
SysClk
Main System Clock input.
3.3V Analog
I
Wire w/ESD
SysReset
Main System Reset.
I/O
5V tolerant
3.3V LVTTL
SysErr
Set to 1 when a Machine Check is generated.
O
5V tolerant
3.3V LVTTL
Halt
Halt from external debugger.
I
5V tolerant
3.3V LVTTL
GPIO0_00:31
System General Purpose I/O.
I/O
5V tolerant
3.3V LVTTL
GPIO1_00:31
Communications General Purpose I/O.
I/O
5V tolerant
3.3V LVTTL
TestEn
Test Enable. Used only for manufacturing tests. Pull down for
normal operation.
I
3.3V LVTTL
Rcvr w/PD
TmrClk
This input must toggle at a rate of less than one half the CPU
core frequency (less than 100MHz in most cases). In most
cases this input toggles much slower (in the 1MHz to 10MHz
I
range).
5V tolerant
3.3V LVTTL
Trace Interface
[TS1E]
[TS2E]
Even Trace execution status.To access this function, software
must toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
[TS1O]
[TS2O]
Odd Trace execution status. To access this function, software
must toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
[TS3:6]
Trace Status. To access this function, software must toggle a
DCR bit.
O
5V tolerant
3.3V LVTTL
[TrcClk]
Trace interface clock. A toggling signal that is always half of
the CPU core frequency. To access this function, software
must toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
Power Pins
GND
Ground
Note: J09-J14, K09-K14, L09-L14, M09-M14, N09-N14, and
I
P09-P14 are also thermal balls.
Hardwire
V_DD
OV_DD
AV_DD
Logic voltage—2.5V
Output driver voltage—3.3V
Filtered PLL voltage—2.5V
I
Hardwire
I
Hardwire
3.3V DC
I
Wire w/ESD
Other Pins
Reserved
Do not connect signals, voltage, or ground to these pins.
n/a
n/a
Notes
1, 2
1
1
1
AMCC Proprietary
DS2011 51