NPE405H Datasheet, PDF (44/70 Pages) Applied Micro Circuits Corporation – PowerNP NPe405H Embedded Processor

NPe405H – PowerNP NPe405H Embedded Processor
Revision 1.01 – April 18, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 2 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.
Signal Name
Description
I/O
Type
PCIGnt1:5
PCIGnt1:5 output when internal arbiter is used.
O
5V tolerant
3.3V PCI
HDLCEX Interface
HDLCEXTxClk
Transmit Clock
I
3.3V LVTTL
HDLCEXTxFS
Transmit Frame Synchronization
I
3.3V LVTTL
HDLCEXTxDataA
Transmit Data port A
O
3.3V LVTTL
HDLCEXTxDataB
Transmit Data port B
O
3.3V LVTTL
HDLCEXRxClk
Receive Clock
I
3.3V LVTTL
HDLCEXRxFS
Receive Frame Synchronization
I
3.3V LVTTL
HDLCEXRxDataA
Receive Data port A
I
3.3V LVTTL
HDLCEXRxDataB
Receive Data port B
I
3.3V LVTTL
[HDLCEXTxEnA]
Transmit Enable port A
O
5V tolerant
3.3V LVTTL
[HDLCEXTxEnB]
Transmit Enable port B
O
5V tolerant
3.3V LVTTL
HDLCMP Interface
HDLCMPTxClk0:3
Transmit Clock signal that controls the transmit bit rate
O
3.3V LVTTL
[HDLCMPTxClk4:7]
Transmit Clock signal that controls the transmit bit rate
O
5V tolerant
3.3V LVTTL
HDLCMPTxData0:3
Transmit Data signal
O
3.3V LVTTL
[HDLCMPTxData4:7]
Transmit Data signal
O
5V tolerant
3.3V LVTTL
[HDLCMPTxEn0:7]
Transmit Data Enable signal that controls when the external
buffer is tri-stated
O
5V tolerant
3.3V LVTTL
HDLCMPRxClk0:3
Receive Clock signal that controls the receive bit rate
I
3.3V LVTTL
[HDLCMPRxClk4:7]
Receive Clock signal that controls the receive bit rate
I
5V tolerant
3.3V LVTTL
HDLCMPRxData0:3
Receive Data signal
I
3.3V LVTTL
[HDLCMPRxData4:7]
Receive Data signal
I
5V tolerant
3.3V LVTTL
Ethernet Interface
EMC0MDClk
Management Data Clock. The MDClk is sourced to the PHY.
Management information is transferred synchronously with
O
respect to this clock (MII, RMII, and SMII).
3.3V LVTTL
EMC0MDIO
Management Data Input/Output is a bidirectional signal
between the Ethernet controller and the PHY. It is used to
transfer control and status information (MII, RMII, and SMII).
I/O
5V tolerant
3.3V LVTTL
Notes
1, 4
44 DS2011
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