NPE405H Datasheet, PDF (12/70 Pages) Applied Micro Circuits Corporation – PowerNP NPe405H Embedded Processor

NPe405H – PowerNP NPe405H Embedded Processor
Revision 1.01 – April 18, 2007
Data Sheet
HDLCEX INTERFACE
• 32-channel HDLC controller
• Two full-duplex Pulse Code Modulation (PCM) Highway ports at speeds up to 4.096 Mbps per port or 8.192
Mbps when using a single port
• Supports HDLC protocol as well as a Transparent mode
• For a single channel per port, autonomous management of I-Frames and S-Frames of the Normal
Response mode (NRM) protocol on one channel per port. U-frames are handled by software.
• Supports software emulation of NRM on all channels
HDLCMP INTERFACE
• HDLC controller provides eight full-duplex serial ports
• Up to 2.048Mbps data rate
• Supports HDLC protocol as well as a Transparent mode
• Software emulation of NRM
GENERAL PURPOSE IO (GPIO) CONTROLLER
• Two GPIO controllers
- 32-signal system GPIO (GPIO0)
- 32-signal communications GPIO (GPIO1)
• Most GPIOs are pin-shared with other functions. Configuration registers are provided to determine whether
a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. Both GPIO func-
tions have 32 I/Os.
• Each GPIO output is separately programmable to emulate an open-drain driver (drives to zero, three-stated
if output bit is 1)
UNIVERSAL INTERRUPT CONTROLLER (UIC)
Two cascaded Universal Interrupt Controllers (UICs) provide the control, status, and communications necessary
for the interrupt sources and the PowerPC processor.
Features include:
• Seven external and 49 internal interrupts
• Edge triggered or level-sensitive
• Positive or negative active
• Selectable non-critical or critical interrupt requests to the PPC405 processor core
• Programmable critical interrupt priority ordering
• Programmable critical interrupt vector generation for reduced latency interrupt handling
12 DS2011
AMCC Proprietary