NPE405H Datasheet, PDF (43/70 Pages) Applied Micro Circuits Corporation – PowerNP NPe405H Embedded Processor

NPe405H – PowerNP NPe405H Embedded Processor
Revision 1.01 – April 18, 2007
Data Sheet
SIGNAL FUNCTIONAL DESCRIPTION
Table 6. Signal Functional Description (Sheet 1 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.
Signal Name
Description
I/O
Type
PCI Interface
PCIAD0:31
PCI Address/Data bus. Multiplexed address and data bus
I/O
5V tolerant
3.3V PCI
PCIC3:0[BE3:0]
PCIParity
PCIFrame
PCI bus command or Byte Enable
I/O
PCI Parity. Parity is even across PCIAD0:31 and
PCIC0:3[BE0:3]. PCIParity is valid one cycle after either an
address or data phase. The PCI device that drove PCIAD0:31
I/O
is responsible for driving PCIParity on the next PCI bus clock.
Driven by the current PCI bus master to indicate the
beginning and duration of a PCI access.
I/O
5V tolerant
3.3V PCI
5V tolerant
3.3V PCI
5V tolerant
3.3V PCI
PCIIRDY
Driven by the current PCI bus master. Assertion of PCIIRDY
indicates that the PCI initiator is ready to transfer data.
I/O
5V tolerant
3.3V PCI
PCITRDY
PCIStop
PCIDevSel
The target of the current PCI transaction drives PCITRDY.
Assertion of PCITRDY indicates that the PCI target is ready to I/O
transfer data.
The target of the current PCI transaction can assert PCIStop
to indicate to the requesting PCI master that it wants to end I/O
the current transaction.
Driven by the target of the current PCI transaction. A PCI
target asserts PCIDevSel when it has decoded an address
I/O
and command encoding and claims the transaction.
5V tolerant
3.3V PCI
5V tolerant
3.3V PCI
5V tolerant
3.3V PCI
PCIIDSel
Used during configuration cycles to select the PCI slave
interface for configuration
I
5V tolerant
3.3V PCI
PCISErr
PCIPErr
PCIClk
Used for reporting address parity errors or catastrophic
failures detected by a PCI target.
I/O
Used for reporting data parity errors on PCI transactions.
PCIPErr is driven active by the device receiving PCIAD0:31,
PCIC0:3[BE0:3], and PCIParity, two PCI clocks following the
I/O
data in which bad parity is detected.
Used as the asynchronous PCI clock.
I
5V tolerant
3.3V PCI
5V tolerant
3.3V PCI
5V tolerant
3.3V PCI
PCIReset
PCI specific reset
O
5V tolerant
3.3V PCI
PCIINT
PCI Interrupt. Open-drain output (two states; 0 or open
circuit).
O
5V tolerant
3.3V PCI
PCIReq0[Gnt]
Req0 when internal arbiter is used, or Gnt when external
arbiter is used. IF PCI bus is used, pull this signal up;
otherwise, pull down.
I
5V tolerant
3.3V PCI
PCIReq1:5
Used as PCIReq1:5 input when internal arbiter is used
I
5V tolerant
3.3V PCI
PCIGnt0[Req]
Gnt0 when internal arbiter is used, or Req when external
arbiter is used
O
5V tolerant
3.3V PCI
Notes
4
4
4
4
4
5
4
4
4
AMCC Proprietary
DS2011 43