NPE405H Datasheet, PDF (6/70 Pages) Applied Micro Circuits Corporation – PowerNP NPe405H Embedded Processor

NPe405H – PowerNP NPe405H Embedded Processor
Revision 1.01 – April 18, 2007
Data Sheet
NPE405H EMBEDDED CONTROLLER FUNCTIONAL BLOCK DIAGRAM
Figure 1. NPe405H Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
x2
Clock
Control
Reset
Power
Mgmt
Timers
MMU
PPC405
Processor Core
8KB
D-Cache
JTAG
DCU
Trace
ICU
DCRs
See Peripheral Interface
DCR Bus
GPIO
x2
IIC IEC
UART
x2
16KB _Arb
I-Cache
On-chip Peripheral Bus (OPB)
DMA
Controller
(4-Channel)
OPB
Bridge
Processor Local Bus (PLB)
MAL0
Ethernet
x4
SDRAM
Controller
13-bit addr
32-bit data
External
Bus
Controller
External
Bus Master PCI Bridge
Controller
MAL1
MAL2
32-bit addr
32-bit data
66 MHz max (async)
HDLCEX
HDLCMP
ZMII
Two
32-channel
ports
8
single-channel
MII, RMII,
ports
SMII
The NPe405H is designed using the IBM Microelectronics Blue Logic™ methodology in which major functional
blocks are integrated to create an application-specific ASIC product. This approach provides a consistent way to
generate complex ASICs using IBM CoreConnect™ Bus Architecture.
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