NPE405H Datasheet, PDF (47/70 Pages) Applied Micro Circuits Corporation – PowerNP NPe405H Embedded Processor

NPe405H – PowerNP NPe405H Embedded Processor
Revision 1.01 – April 18, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 5 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.
Signal Name
Description
I/O
Type
DQMCB
DQM for ECC check bits.
O
3.3V LVTTL
ECC0:7
ECC check bits 0:7.
I/O 3.3V LVTTL
BankSel0:3
Select up to four external SDRAM banks.
O
3.3V LVTTL
WE
Write Enable.
O
3.3V LVTTL
ClkEn0:1
SDRAM Clock Enable.
O
3.3V LVTTL
MemClkOut0:1
Two copies of an SDRAM clock allows, in some cases,
glueless SDRAM attachment without requiring this signal to
O
3.3V LVTTL
be repowered by a PLL or zero-delay buffer.
External Slave Peripheral Bus Interface
PerData00:31
External peripheral data bus when not in external master
mode, otherwise used by external master.
I/O
Note: PerData00 is the most significant bit (msb) on this bus.
5V tolerant
3.3V LVTTL
PerAddr00:31
External peripheral address bus when not in external master
mode, otherwise used by external master.
I/O
5V tolerant
3.3V LVTTL
PerPar0:3
External peripheral byte parity signals.
I/O
5V tolerant
3.3V LVTTL
PerWBE0:3
Peripheral write-bte enable. Byte-enables which are valid for
an entire cycle or write-byte-enables which are valid for each
byte on each data transfer, allowing partial word transactions.
Used by either external bus controller or DMA controller
I/O
depending upon the type of transfer involved. Used as inputs
when external bus master owns the external interface.
5V tolerant
3.3V LVTTL
[PerWE]
Peripheral write enable. Low when any of the four PerWBE
signals are low.
I/O
5V tolerant
3.3V LVTTL
PerCS0
[PerCS1:7]
Peripheral Chip Selects
O
5V tolerant
3.3V LVTTL
PerOE
Peripheral output enable. Used by either the external bus
controller or the DMA controller depending upon the type of
transfer involved. When the NPe405H is the bus master, it
O
5V tolerant
3.3V LVTTL
enables the peripherals to drive the bus.
PerR/W
Peripheral read/write. Used when not in external master mode
by either the external bus controller or DMA controller
depending upon the type of transfer involved. High indicates a
read from memory, low indicates a write to memory.
I/O
Otherwise it used by the external master as an input to
indicate the direction of transfer.
5V tolerant
3.3V LVTTL
PerReady
Indicates peripheral is ready to transfer data.
I
5V tolerant
3.3V LVTTL
PerBLast
Peripheral burst last. Used to indicate the last transfer of a
memory access.
I/O
5V tolerant
3.3V LVTTL
PerClk
Peripheral Clock. Used by an external master and by
synchronous peripheral slaves.
O
5V tolerant
3.3V LVTTL
PerErr
Used to indicate errors from peripherals.
I
5V tolerant
3.3V LVTTL
Notes
1
1
1
1, 2, 7
7
7
1
1
1, 7
1, 5
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