NPE405H Datasheet, PDF (56/70 Pages) Applied Micro Circuits Corporation – PowerNP NPe405H Embedded Processor

NPe405H – PowerNP NPe405H Embedded Processor
Revision 1.01 – April 18, 2007
Data Sheet
CLOCKING SPECIFICATIONS
Table 12. Clocking Specifications
Symbol
Parameter
SysClk Input
F_C
SysClk clock input frequency
T_C
SysClk clock period
T_CS
Clock edge stability (phase jitter, cycle to cycle)
T_CH
Clock input high time
T_CL
Clock input low time
Note:Input slew rate > 2V/ns
MemClkOut Output
F_C
MemClkOut clock output frequency–133MHz
T_C
MemClkOut clock period–133MHz
F_C
MemClkOut clock output frequency–200MHz
T_C
MemClkOut clock period–200MHz
F_C
MemClkOut clock output frequency–266MHz
T_C
MemClkOut clock period–266MHz
T_CH
Clock output high time
T_CL
Clock output low time
Other Clocks
F_C
VCO frequency
F_C
PLB frequency–133MHz
F_C
PLB frequency–200MHz
F_C
PLB frequency–266MHz
F_C
OPB frequency–133MHz
F_C
OPB frequency–200MHz
F_C
OPB frequency–266MHz
Notes:
1. If HDLCEX is not used, the maximum OPB frequency is 66.66MHz.
CLOCKING WAVEFORM
Min
Max
Units
25
15
40% of nominal period
40% of nominal period
66.66
40
0.15
60% of nominal period
60% of nominal period
MHz
ns
ns
ns
ns
15
10
7.5
45% of nominal period
45% of nominal period
66.66
100
133.33
55% of nominal period
55% of nominal period
MHz
ns
MHz
ns
MHz
ns
ns
ns
400
800
MHz
66.66
MHz
100
MHz
133.33
MHz
50¹
MHz
50
MHz
50¹
MHz
Figure 4. Clocking Waveform
T_CH
T_CL
T_C
2.0V
1.5V
0.8V
56 DS2011
AMCC Proprietary