NPE405H Datasheet, PDF (61/70 Pages) Applied Micro Circuits Corporation – PowerNP NPe405H Embedded Processor

NPe405H – PowerNP NPe405H Embedded Processor
Revision 1.01 – April 18, 2007
Data Sheet
Table 14. I/O Specifications—All (Sheet 2 of 2)
Notes:
1. PCI timings are for asynchronous operation up to 66MHz. PCI output hold time requirement is 1ns for 66MHz and 2ns for
33 MHz.
Signal
JTAG Interface
TCK
TDI
TDO
TMS
TRST
System Interface
GPIO0:1
Halt
SysClk
SysErr
SysReset
TestEn
TmrClk
Input (ns)
Setup Time Hold Time
(T_IS min) (T_IH min)
Output (ns)
Valid Delay Hold Time
(T_OV max) (T_OH min)
Output Current (mA)
I/O H
I/O L
(maximum) (minimum)
Clock
async
async
n/a
n/a
n/a
n/a
async
async
n/a
n/a
n/a
n/a
n/a
n/a
async
async
12
8
async
async
n/a
n/a
n/a
n/a
async
async
n/a
n/a
n/a
n/a
na
na
na
na
12
8
async
async
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
8.6
3.7
12
8
n/a
n/a
7.4
3.3
12
8
dc
dc
n/a
n/a
n/a
n/a
n/a
n/a
async
async
n/a
n/a
Notes
AMCC Proprietary
DS2011 61