NPE405H Datasheet, PDF (45/70 Pages) Applied Micro Circuits Corporation – PowerNP NPe405H Embedded Processor

NPe405H – PowerNP NPe405H Embedded Processor
Revision 1.01 – April 18, 2007
Data Sheet
Table 6. Signal Functional Description (Sheet 3 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.
Signal Name
Description
I/O
Type
EMC0TxD0[EMC0Tx0D0][EMC0Tx0D]
EMC0TxD1[EMC0Tx0D1][EMC0Tx1D]
EMC0TxD2[EMC0Tx1D0][EMC0Tx2D]
EMC0TxD3[EMC0Tx1D1][EMC0Tx3D]
Transmit Data. A nibble wide data bus towards the net. The
data is synchronous with PHY0TxClk (MII 0[RMII 0, 1][SMII 0,
1, 2, 3]).
O
3.3V LVTTL
[EMC1TxD0][EMC1Tx2D0]
[EMC1TxD1][EMC1Tx2D1]
[EMC1TxD2][EMC1Tx3D0]
[EMC1TxD3][EMC1Tx3D1]
RMII Transmit Data (MII 1[RMII 2, 3]).
O
5V tolerant
3.3V LVTTL
Transmit Enable. This signal is driven by EMAC2 to the PHY.
Data is valid during the active state of this signal. Deassertion
of this signal indicates end of frame transmission. This signal
EMC0TxEn[EMC0Tx0En][EMC0Sync] _{is synchronous with PHYTxClk (MII 0[RMII 0]).}
O
or
SMII Sync.
3.3V LVTTL
EMC0TxErr[EMC0Tx1En]
Transmit Error. This signal is generated by the Ethernet
controller, is connected to the PHY and is synchronous with
the PHY0TxClk. It informs the PHY that an error was detected
(MII 0).
O
or
Transmit Enable [RMII 1].
3.3V LVTTL
[EMC1TxEn][EMC1Tx2En]
Transmit Enable ([MII 1][RMII 2]).
O
5V tolerant
3.3V LVTTL
[EMC1TxErr][EMC1Tx3En]
Transmit Error. This signal is generated by the Ethernet
controller, is connected to the PHY and is synchronous with
the PHY1TxClk. It informs the PHY that an error was detected
([MII 1]).
O
or
Transmit Enable [RMII 3].
5V tolerant
3.3V LVTTL
PHY0Col[PHY0Rx1Er]l
Collision [receive error] signal from the PHY. This is an
asynchronous signal (MII 0).
or
Receive Error ([RMII 1]).
I
5V tolerant
3.3V LVTTL
PHY0CrS[PHY0CrS0DV]
Carrier Sense signal from the PHY. This is an asynchronous
signal (MII 0).
or
I
5V tolerant
3.3V LVTTL
Carrier sense data valid ([RMII 0]).
PHY0RxClk
Receiver medium clock. This signal is generated by the PHY
(MII 0).
I
5V tolerant
3.3V LVTTL
PHY0RxD0[PHY0Rx0D0][PHY0Rx0D]
PHY0RxD1[PHY0Rx0D1][PHY0Rx1D]
PHY0RxD2[PHY0Rx1D0][PHY0Rx2D]
PHY0RxD3[PHY0Rx1D1][PHY0Rx3D]
Received Data. This is a nibble wide bus from the PHY. The
data is synchronous with PHY0RxClk (MII 0[RMII 0, 1][SMII 0,
1, 2, 3]).
I
5V tolerant
3.3V LVTTL
[PHY1RxD0][PHY1Rx2D0]
[PHY1RxD1][PHY1Rx2D1]
[PHY1RxD2][PHY1Rx3D0]
[PHY1RxD3][PHY1Rx3D1]
Receive Data (MII 1[RMII 2, 3]).
I
5V tolerant
3.3V LVTTL
Notes
1, 5
1, 4
1, 4
AMCC Proprietary
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