NPE405H Datasheet, PDF (11/70 Pages) Applied Micro Circuits Corporation – PowerNP NPe405H Embedded Processor

NPe405H – PowerNP NPe405H Embedded Processor
Revision 1.01 – April 18, 2007
Data Sheet
DMA CONTROLLER
• Supports the following transfers:
- Memory-to-memory transfers
- Buffered peripheral to memory transfers
- Buffered memory to peripheral transfers
• Four channels
• Scatter/Gather capability for programming multiple DMA operations
• 8-, 16-, 32-bit peripheral support (OPB and external bus attached)
• 32-bit addressing
• Address increment or decrement
• Internal 32-byte data buffering capability
• Supports internal and external peripherals
• Support for memory mapped peripherals
• Support for peripherals running on slower frequency buses
SERIAL INTERFACE
• Two 8-pin UART interfaces provided
• Selectable internal or external serial clock to allow wide range of baud rates
• Register compatibility with NS16550 register set
• Complete status reporting capability
• Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA engine
IIC BUS INTERFACE
• Compliant with Phillips® Semiconductors I²C Specification, dated 1995
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed V_DD IIC interface
• Two independent 4 x 1 byte data buffers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocol
• Programmable error recovery
IIC EEPROM CONTROLLER
Supports setting of processor configuration from serial EEPROM during system reset.
AMCC Proprietary
DS2011 11