EPF8452ATC100-4N Datasheet, PDF (62/62 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 8000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1) Perform a complete thermal analysis before committing a design to this device package. See Application Note 74
(Evaluating Power for Altera Devices) for more information.
(2) This pin is a dedicated pin and is not available as a user I/O pin.
(3) SDOUT will drive out during configuration. After configuration, it may be used as a user I/O pin. By default, the
MAX+PLUS II software will not use SDOUT as a user I/O pin; the user can override the MAX+PLUS II software and
use SDOUT as a user I/O pin.
(4) If the device is not configured to use the JTAG BST circuitry, this pin is available as a user I/O pin.
(5) JTAG pins are available for EPF8636A devices only. These pins are dedicated user I/O pins.
(6) If this pin is used as an input in user mode, ensure that it does not toggle before or during configuration.
(7) TRST is a dedicated input pin for JTAG use. This pin must be grounded if JTAG BST is not used.
(8) Pin 52 is a V_CC pin on EPF8452A devices only.
(9) The user I/O pin count includes dedicated input pins and all I/O pins.
(10) Unused dedicated inputs should be tied to ground on the board.
(11) SDOUT does not exist in the EPF8636GC192 device.
(12) These pins are no connect (N.C.) pins for EPF8636A devices only. They are user I/O pins in EPF8820A devices.
(13) EPF8636A devices have 132 user I/O pins; EPF8820A devices have 148 user I/O pins.
(14) For EPF81500A devices, these pins are dedicated JTAG pins and are not available as user I/O pins. If JTAG BST is
not used, TDI, TCK, TMS, and TRST should be tied to GND.
Revision
History
The information contained in the FLEX 8000 Programmable Logic Device
Family Data Sheet version 11.1 supersedes information published in
previous versions. The FLEX 8000 Programmable Logic Device Family Data
Sheet version 11.1 contains the following change: minor textual updates.
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