EPF8452ATC100-4N Datasheet, PDF (6/62 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 8000 Programmable Logic Device Family Data Sheet
Logic Array Block
A logic array block (LAB) consists of eight LEs, their associated carry and
cascade chains, LAB control signals, and the LAB local interconnect. The
LAB provides the coarse-grained structure of the FLEX 8000 architecture.
This structure enables FLEX 8000 devices to provide efficient routing,
high device utilization, and high performance. Figure 2 shows a block
diagram of the FLEX 8000 LAB.
Figure 2. FLEX 8000 Logic Array Block
Dedicated
Inputs
Row Interconnect
LAB Local
Interconnect
(32 channels)
LAB Control
Signals
24
4
4
4
4
4
4
4
4
4
8
6
4
Carry-In and
Cascade-In
from LAB
on Left
4
2
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
8
8 16
2
Carry-Out and
Cascade-Out
to LAB on Right
See Figure 8
for details.
Column-to-Row
Interconnect
Column
Interconnect
Altera Corporation