EPF8452ATC100-4N Datasheet, PDF (33/62 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 8000 Programmable Logic Device Family Data Sheet
Table 17. FLEX 8000 Internal Timing Parameters Note (1)
Symbol
Parameter
t _IOD
IOE register data delay
t _IOC
IOE register control signal delay
t _IOE
Output enable delay
t _IOCO
IOE register clock-to-output delay
t _IOCOMB
IOE combinatorial delay
t _IOSU
IOE register setup time before clock; IOE register recovery time after asynchronous clear
t _IOH
IOE register hold time after clock
t _IOCLR
IOE register clear delay
t _IN
Input pad and buffer delay
t _OD1
Output buffer and pad delay, slow slew rate = off, V_CCIO = 5.0 V C1 = 35 pF (2)
t _OD2
Output buffer and pad delay, slow slew rate = off, V_CCIO = 3.3 V C1 = 35 pF (2)
t _OD3
Output buffer and pad delay, slow slew rate = on, C1 = 35 pF (3)
t _XZ
Output buffer disable delay, C1 = 5 pF
t _ZX1
Output buffer enable delay, slow slew rate = off, V_CCIO = 5.0 V, C1 = 35 pF (2)
3
t _ZX2
Output buffer enable delay, slow slew rate = off, V_CCIO = 3.3 V, C1 = 35 pF (2)
t _ZX3
Output buffer enable delay, slow slew rate = on, C1 = 35 pF (3)
Table 18. FLEX 8000 LE Timing Parameters Note (1)
Symbol
Parameter
t _LUT
t _CLUT
t _RLUT
t _GATE
t _CASC
t _CICO
t _CGEN
t _CGENR
t_C
t _CH
t _CL
t _CO
t _COMB
t _SU
t_H
t _PRE
t _CLR
LUT delay for data-in
LUT delay for carry-in
LUT delay for LE register feedback
Cascade gate delay
Cascade chain routing delay
Carry-in to carry-out delay
Data-in to carry-out delay
LE register feedback to carry-out delay
LE register control signal delay
LE register clock high time
LE register clock low time
LE register clock-to-output delay
Combinatorial delay
LE register setup time before clock; LE register recovery time after asynchronous preset, clear, or
load
LE register hold time after clock
LE register preset delay
LE register clear delay
Altera Corporation
33