EPF8452ATC100-4N Datasheet, PDF (35/62 Pages) Altera Corporation – Programmable Logic Device Family

Carry-In from
Previous LE
t_ROW
Cascade-In from
Previous LE
t_LOCAL
LUT Delay
t_LUT
t_RLUT
t_CLUT
Carry Chain
Delay
t_CGEN
t_CGENR
t_CICO
Cascade
Gate Delay
t_GATE
LE
Register
Delays
t_CO
t_COMB
t_SU
t_H
t_PRE
t_CLR
LE-Out
t_COL
Register
Control
t_C
t_CASC
Cascade
Routing Delay
Dedicated
Input Delays
t_{DIN_D}
t_{DIN_C}
t_{DIN_IO}
t_LABCARRY
t_LABCASC
Carry-Out Carry-Out
to Next LE to Next LE
in Same in Next
LAB
LAB
Cascade-Out Cascade-Out
to Next LE in to Next LE in
Next LAB Same LAB
Output Data
Delay
t_IOD
I/O Register
Control
t_IOC
t_IOE
I/O Register
Delays
t_IOCO
t_IOCOMB
t_IOSU
t_IOH
t_IOCLR
Data-In
IOE
Output
Delays
t_OD1
t_OD2
t_OD3
t_XZ
t_ZX1
t_ZX2
t_ZX3
I/O Pin
Input
Delay
t_IN