EPF8452ATC100-4N Datasheet, PDF (34/62 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 8000 Programmable Logic Device Family Data Sheet
Table 19. FLEX 8000 Interconnect Timing Parameters Note (1)
Symbol
t _LABCASC
t _LABCARRY
t _LOCAL
t _ROW
t _COL
t _{DIN_C}
t _{DIN_D}
t _{DIN_IO}
Parameter
Cascade delay between LEs in different LABs
Carry delay between LEs in different LABs
LAB local interconnect delay
Row interconnect routing delay (4)
Column interconnect routing delay
Dedicated input to LE control delay
Dedicated input to LE data delay (4)
Dedicated input to IOE control delay
Table 20. FLEX 8000 External Reference Timing Characteristics Note (5)
Symbol
Parameter
t _DRR
t_ODH
Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local interconnects (6)
Output data hold time after clock (7)
Notes to tables:
(1) Internal timing parameters cannot be measured explicitly. They are worst-case delays based on testable and
external parameters specified by Altera. Internal timing parameters should be used for estimating device
performance. Post-compilation timing simulation or timing analysis is required to determine actual worst-case
performance.
(2) These values are specified in Table 10 on page 28 or Table 14 on page 29.
(3) For the t_OD3 and t_ZX3 parameters, V_CCIO = 3.3 V or 5.0 V.
(4) The t_ROW and t_{DIN_D} delays are worst-case values for typical applications. Post-compilation timing simulation or
timing analysis is required to determine actual worst-case performance.
(5) External reference timing characteristics are factory-tested, worst-case values specified by Altera. A representative
subset of signal paths is tested to approximate typical device applications.
(6) For more information on test conditions, see Application Note 76 (Understanding FLEX 8000 Timing).
(7) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies to global and non-global clocking, and for LE and I/O element registers.
The FLEX 8000 timing model shows the delays for various paths and
functions in the circuit. See Figure 19. This model contains three distinct
parts: the LE; the IOE; and the interconnect, including the row and column
FastTrack Interconnect, LAB local interconnect, and carry and cascade
interconnect paths. Each parameter shown in Figure 19 is expressed as a
worst-case value in Tables 22 through 49. Hand-calculations that use the
FLEX 8000 timing model and these timing parameters can be used to
estimate FLEX 8000 device performance. Timing simulation or timing
analysis after compilation is required to determine the final worst-case
performance. Table 21 summarizes the interconnect paths shown in
Figure 19.
f For more information on timing parameters, go to Application Note 76
(Understanding FLEX 8000 Timing).
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Altera Corporation