EPF8452ATC100-4N Datasheet, PDF (36/62 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 8000 Programmable Logic Device Family Data Sheet
Table 21. FLEX 8000 Timing Model Interconnect Paths
Source
LE-Out
LE-Out
LE-Out
LE-Out
LE-Out
IOE on row
IOE on column
Destination
LE in same LAB
LE in same row, different LAB
LE in different row
IOE on column
IOE on row
LE in same row
Any LE
Total Delay
t _LOCAL
t _ROW + t_LOCAL
t _COL + t_ROW + t_LOCAL
t _COL
t _ROW
t _ROW + t_LOCAL
t _COL + t_ROW + t_LOCAL
Tables 22 through 49 show the FLEX 8000 internal and external timing
parameters.
Table 22. EPF8282A Internal I/O Element Timing Parameters
Symbol
t _IOD
t _IOC
t _IOE
t_IOCO
t _IOCOMB
t _IOSU
t _IOH
t _IOCLR
t _IN
t _OD1
t _OD2
t _OD3
t _XZ
t _ZX1
t _ZX2
t _ZX3
A-2
Min
Max
0.7
1.7
1.7
1.0
0.3
1.4
0.0
1.2
1.5
1.1
–
4.6
1.4
1.4
–
4.9
Speed Grade
A-3
Min
Max
0.8
1.8
1.8
1.0
0.2
1.6
0.0
1.2
1.6
1.4
–
4.9
1.6
1.6
–
5.1
Unit
A-4
Min
Max
0.9
ns
1.9
ns
1.9
ns
1.0
ns
0.1
ns
1.8
ns
0.0
ns
1.2
ns
1.7
ns
1.7
ns
–
ns
5.2
ns
1.8
ns
1.8
ns
–
ns
5.3
ns
36
Altera Corporation