EPF8452ATC100-4N Datasheet, PDF (26/62 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 8000 Programmable Logic Device Family Data Sheet
f
Generic Testing
Table 8. JTAG Timing Parameters & Values
Symbol
Parameter
t_JCP
t_JCH
t_JCL
t_JPSU
t_JPH
t_JPCO
t_JPZX
t_JPXZ
t_JSSU
t_JSH
t_JSCO
t_JSZX
t_JSXZ
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high-impedance to valid output
JTAG port valid output to high-impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high-impedance to valid output
Update register valid output to high-impedance
EPF8282A Unit
EPF8282AV
EPF8636A
EPF8820A
EPF81500A
Min Max
100
ns
50
ns
50
ns
20
ns
45
ns
25 ns
25 ns
25 ns
20
ns
45
ns
35 ns
35 ns
35 ns
For detailed information on JTAG operation in FLEX 8000 devices, refer to
Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera
Devices).
Each FLEX 8000 device is functionally tested and specified by Altera.
Complete testing of each configurable SRAM bit and all logic
functionality ensures 100% configuration yield. AC test measurements for
FLEX 8000 devices are made under conditions equivalent to those shown
in Figure 15. Designers can use multiple test patterns to configure devices
during all stages of the production flow.
26
Altera Corporation