EPF8452ATC100-4N Datasheet, PDF (18/62 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 8000 Programmable Logic Device Family Data Sheet
Figure 9. FLEX 8000 Device Interconnect Resources
Each LAB is named according to its physical row (A, B, C, etc.) and column (1, 2, 3, etc.) position within the device.
See Figure 12
for details.
1 IOE
IOE
Column
Interconnect
IOE
Row
Interconnect
IOE IOE
See Figure 11
for details.
IOE 1
8 IOE
IOE 8
LAB
LAB
A1
A2
1 IOE
8 IOE
IOE 1
IOE 8
LAB
B1
LAB Local
Interconnect
LAB
B2
Cascade &
Carry Chain
IOE IOE
IOE IOE
I/O Element
An IOE contains a bidirectional I/O buffer and a register that can be used
either as an input register for external data that requires a fast setup time,
or as an output register for data that requires fast clock-to-output
performance. IOEs can be used as input, output, or bidirectional pins. The
MAX+PLUS II Compiler uses the programmable inversion option to
automatically invert signals from the row and column interconnect where
appropriate. Figure 10 shows the IOE block diagram.
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Altera Corporation