EPF8452ATC100-4N Datasheet, PDF (32/62 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 8000 Programmable Logic Device Family Data Sheet
Figure 18. Output Drive Characteristics of EPF8282AV Devices
100
75
Typical I_O
Output
50
Current (mA)
25
I_OL
V_CC = 3.3 V
Room Temperature
I_OH
Timing Model
1
2
3
4
Output Voltage (V)
The continuous, high-performance FastTrack Interconnect routing
structure ensures predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a segmented connection scheme and hence have
unpredictable performance. Timing simulation and delay prediction are
available with the MAX+PLUS II Simulator and Timing Analyzer, or with
industry-standard EDA tools. The Simulator offers both pre-synthesis
functional simulation to evaluate logic design accuracy and post-
synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer
provides point-to-point timing delay information, setup and hold time
prediction, and device-wide performance analysis.
Tables 17 through 20 describe the FLEX 8000 timing parameters and their
symbols.
32
Altera Corporation