EPF8452ATC100-4N Datasheet, PDF (21/62 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 8000 Programmable Logic Device Family Data Sheet
Figure 12. FLEX 8000 Column-to-IOE Connections
Each IOE is
driven by an
IOE
IOE
8-to-1
multiplexer.
Each IOE can drive
up to two column
signals.
8
8
Altera Corporation
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Column Interconnect
In addition to general-purpose I/O pins, FLEX 8000 devices have four
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dedicated input pins. These dedicated inputs provide low-skew, device-
wide signal distribution, and are typically used for global clock, clear, and
preset control signals. The signals from the dedicated inputs are available
as control signals for all LABs and I/O elements in the device. The
dedicated inputs can also be used as general-purpose data inputs because
they can feed the local interconnect of each LAB in the device.
Signals enter the FLEX 8000 device either from the I/O pins that provide
general-purpose input capability or from the four dedicated inputs. The
IOEs are located at the ends of the row and column interconnect channels.
I/O pins can be used as input, output, or bidirectional pins. Each I/O pin
has a register that can be used either as an input register for external data
that requires fast setup times, or as an output register for data that
requires fast clock-to-output performance. The MAX+PLUS II Compiler
uses the programmable inversion option to invert signals automatically
from the row and column interconnect when appropriate.
The clock, clear, and output enable controls for the IOEs are provided by
a network of I/O control signals. These signals can be supplied by either
the dedicated input pins or by internal logic. The IOE control-signal paths
are designed to minimize the skew across the device. All control-signal
sources are buffered onto high-speed drivers that drive the signals around
the periphery of the device. This “peripheral bus” can be configured to
provide up to four output enable signals (10 in EPF81500A devices), and
up to two clock or clear signals. Figure 13 on page 22 shows how two
output enable signals are shared with one clock and one clear signal.
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