EPF8452ATC100-4N Datasheet, PDF (23/62 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 8000 Programmable Logic Device Family Data Sheet
Table 5 lists the source of the peripheral control signal for each FLEX 8000
device by row.
Table 5. Row Sources of FLEX 8000 Peripheral Control Signals
Peripheral EPF8282A
EPF8452A
Control Signal EPF8282AV
EPF8636A
EPF8820A EPF81188A EPF81500A
CLK0
Row A
Row A
Row A
Row A
Row E
Row E
CLK1/OE1
Row B
Row B
Row C
Row C
Row B
Row B
CLR0
Row A
Row A
Row B
Row B
Row F
Row F
CLR1/OE0
Row B
Row B
Row C
Row D
Row C
Row C
OE2
Row A
Row A
Row A
Row A
Row D
Row A
OE3
Row B
Row B
Row B
Row B
Row A
Row A
OE4
–
–
–
–
–
Row B
OE5
–
–
–
–
–
Row C
OE6
OE7
–
–
–
–
–
–
–
–
–
–
Row D
Row D
3
OE8
–
–
–
–
–
Row E
OE9
–
–
–
–
–
Row F
Output
Configuration
f
This section discusses slew-rate control and MultiVolt I/O interface
operation for FLEX 8000 devices.
Slew-Rate Control
The output buffer in each IOE has an adjustable output slew rate that can
be configured for low-noise or high-speed performance. A slow slew rate
reduces system noise by slowing signal transitions, adding a maximum
delay of 3.5 ns. The slow slew-rate setting affects only the falling edge of
a signal. The fast slew rate should be used for speed-critical outputs in
systems that are adequately protected against noise. Designers can specify
the slew rate on a pin-by-pin basis during design entry or assign a default
slew rate to all pins on a global basis.
For more information on high-speed system design, go to Application
Note 75 (High-Speed Board Designs).
Altera Corporation
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