EPF8452ATC100-4N Datasheet, PDF (5/62 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 8000 Programmable Logic Device Family Data Sheet
Figure 1 shows a block diagram of the FLEX 8000 architecture. Each group
of eight LEs is combined into an LAB; LABs are arranged into rows and
columns. The I/O pins are supported by I/O elements (IOEs) located at
the ends of rows and columns. Each IOE contains a bidirectional I/O
buffer and a flipflop that can be used as either an input or output register.
Figure 1. FLEX 8000 Device Block Diagram
I/O Element
(IOE)
IOE IOE
IOE IOE
IOE
IOE
Logic Array
Block (LAB)
IOE
IOE
Logic
Element (LE)
IOE
IOE
FastTrack
Interconnect
IOE
3
IOE
IOE IOE
IOE IOE
Signal interconnections within FLEX 8000 devices and between device
pins are provided by the FastTrack Interconnect, a series of fast,
continuous channels that run the entire length and width of the device.
IOEs are located at the end of each row (horizontal) and column (vertical)
FastTrack Interconnect path.
Altera Corporation
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