AK4646EZ Datasheet, PDF (73/78 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/SPK-AMP

[AK4646EZ]
■ Mono signal output from Speaker-Amp
CLOCK
Clocks can be stopped.
PMBP bit
(Addr:00H, D5)
PMSPK bit
(Addr:00H, D4)
DACS bit
(Addr:02H, D5)
BEEPS bit
(Addr:02H, D6)
SPPSN bit
(Addr:02H, D7)
SPP pin
(1)
" 0" or " 1"
0
(2)
(3)
(4)
Hi-Z
Normal Output
(5)
(6)
Hi-Z
Example:
(1) Addr:00H, Data:70H
(2) Addr:02H, Data:60H
(3) Addr:02H, Data:E0H
Mono Signal Output
(4) Addr:02H, Data:60H
(5) Addr:00H, Data:40H
SPN pin
Hi-Z
SVDD/2 Normal Output SVDD/2 Hi-Z
(6) Addr:02H, Data:00H
Figure 44. “MIN-Amp Æ Speaker-Amp” Output Sequence
<Example>
The clocks can be stopped when only MIN-Amp and Speaker-Amp are operating.
(1) Power Up MIN-Amp and Speaker-Amp: PMBP = PMSPK bits = “0” → “1”
(2) Disable the path of “DAC Æ SPK-Amp”: DACS bit = “0”
Enable the path of “MIN Æ SPK-Amp”: BEEPS bit = “0” → “1”
(3) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”
“(3)” time depends on the time constant of external resistor and capacitor connected to MIN pin. If
Speaker-Amp output is enabled before input of MIN-Amp becomes stable, pop noise may occur.
e.g. R=20k, C=0.1μF: Recommended wait time is more than 5τ = 10ms.
(4) Enter the power-save-mode of Speaker-Amp: SPPSN bit = “1” → “0”
(5) Power Down MIN-Amp and Speaker-Amp: PMBP = PMSPK bits = “1” → “0”
(6) Disable the path of “MIN Æ SPK-Amp”: BEEPS bit = “1” → “0”
MS0630-E-00
- 73 -
2007/06