AK4646EZ Datasheet, PDF (42/78 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/SPK-AMP

[AK4646EZ]
Register Name
LMTH1-0
ZELMN
ZTM1-0
WTM2-0
OREF5-0
OVL7-0,
OVR7-0
LMAT1-0
LFST
RGAIN1-0
RFST1-0
ALC2
Comment
fs=8kHz
Data
Operation
Limiter detection Level
01
−4.1dBFS
Limiter zero crossing detection
0
Enable
Zero crossing timeout period
01
32ms
Recovery waiting period
*WTM2-0 bits should be the same data 001
32ms
as ZTM1-0 bits
Maximum gain at recovery operation 28H
+6dB
Gain of VOL
91H
0dB
Limiter ATT step
00
1 step
Fast Limiter Operation
1
ON
Recovery GAIN step
00
1 step
Fast Recovery Speed
00
4 times
ALC enable
1
Enable
Table 33. Example of the ALC Setting (Playback)
fs=44.1kHz
Data
Operation
01
−4.1dBFS
0
Enable
11
23.2ms
100
46.4ms
28H
+6dB
91H
0dB
00
1 step
1
ON
00
1 step
00
4 times
1
Enable
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0” or PMADL=PMADR bits = “0”.
• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0, LFST
Manual Mode
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 32ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC bit = “1”
WR (ZTM1-0, WTM2-0, RFST1-0)
(1) Addr=06H, Data=14H
WR (IREF7-0)
WR (IVL/R7-0) ^{* The value of IVOL should be}
the same or smaller than REF’s
WR (RGAIN1, LMTH1)
(2) Addr=08H, Data=E1H
(3) Addr=09H&0CH, Data=E1H
(4) Addr=0BH, Data=28H
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”)
(5) Addr=07H, Data=21H
ALC Operation
Note : WR : Write
Figure 29. Registers set-up sequence at ALC operation
MS0630-E-00
- 42 -
2007/06