AK4646EZ Datasheet, PDF (14/78 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/SPK-AMP

[AK4646EZ]
Parameter
Symbol
min
Audio Interface Timing
Master Mode
BICK “↓” to LRCK Edge (Note 27)
LRCK Edge to SDTO (MSB)
(Except I²S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
tMBLR
−40
tLRD
−70
tBSD
−70
tSDH
50
tSDS
50
Slave Mode
LRCK Edge to BICK “↑” (Note 27)
BICK “↑” to LRCK Edge (Note 27)
LRCK Edge to SDTO (MSB)
(Except I²S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
tLRB
50
tBLR
50
tLRD
-
tBSD
-
tSDH
50
tSDS
50
Control Interface Timing
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTIO Setup Time
tCDS
40
CDTIO Hold Time
tCDH
40
CSN “H” Time
tCSW
150
CSN Edge to CCLK “↑” (Note 28)
CCLK “↑” to CSN Edge (Note 28)
CCLK “↓” to CDTIO (at Read Command)
CSN “↑” to CDTIO (Hi-Z) (at Read Command)
tCSS
50
tCSH
50
tDCD
-
tCCZ
-
Power-down & Reset Timing
PDN Pulse Width
(Note 29)
tPD
150
PMADL or PMADR “↑“ to SDTO valid (Note 30)
tPDV
-
Note 27. BICK rising edge must not occur at the same time as LRCK edge.
Note 28. CCLK rising edge must not occur at the same time as CSN edge.
Note 29. The AK4646 can be reset by the PDN pin = “L”.
Note 30. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1059
max Units
40
ns
70
ns
70
ns
-
ns
-
ns
-
ns
-
ns
80
ns
80
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
70
ns
70
ns
-
ns
-
1/fs
MS0630-E-00
- 14 -
2007/06