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| AK4646EZ Datasheet, PDF (21/78 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/SPK-AMP | |||
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[AK4646EZ]
â PLL Unlock State
1) PLL Master Mode (PMPLL bit = â1â, M/S bit = â1â)
In this mode, LRCK and BICK pins go to âLâ and irregular frequency clock is output from MCKO pins at MCKO bit is
â1â before the PLL goes to lock state after PMPLL bit = â0â Ã â1â. If MCKO bit is â0â, MCKO pin goes to âLâ (Table
7).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to âLâ by
setting PMPLL bit to â0â.
PLL State
After that PMPLL bit â0â Ã â1â
MCKO pin
MCKO bit = â0â MCKO bit = â1â
âLâ Output
Invalid
BICK pin
âLâ Output
PLL Unlock (except the case above)
âLâ Output
Invalid
Invalid
PLL Lock
âLâ Output
Table 9
Table 10
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = â1â, M/S bit = â1â)
LRCK pin
âLâ Output
Invalid
1fs Output
2) PLL Slave Mode (PMPLL bit = â1â, M/S bit = â0â)
In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = â0â Ã â1â.
Then, the clock selected by Table 9 is output from MCKO pin when PLL is locked. ADC and DAC output invalid data
when the PLL is unlocked. For DAC, the output signal should be muted by writing â0â to DACL and DACS bits.
PLL State
After that PMPLL bit â0â Ã â1â
MCKO pin
MCKO bit = â0â MCKO bit = â1â
âLâ Output
Invalid
PLL Unlock
âLâ Output
Invalid
PLL Lock
âLâ Output
Output
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = â0â, M/S bit = â0â)
MS0630-E-00
- 21 -
2007/06
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