AK4646EZ Datasheet, PDF (72/78 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/SPK-AMP

[AK4646EZ]
■ Speaker-amp Output
FS3-0 bits
0,000
(Addr:05H, D5&D2-0)
DACS bit
(Addr:02H, D3)
(1)
(2)
1,111
SPKG1-0 bits
(Addr:03H, D4-3)
ALC Control 1
(Addr:06H)
ALC Control 2
(Addr:0BH)
ALC2 bit
(Addr:07H, D6)
OVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
PMDAC bit
(Addr:00H, D2)
00
00H
28H
0
(3)
(4)
(5)
(6)
91H
(7)
01
3CH
28H
X
91H
PMBP bit
(Addr:00H, D5)
PMSPK bit
(Addr:00H, D4)
SPPSN bit
(Addr:02H, D7)
SPP pin
(8)
Hi-Z
(9)
(10)
Normal Output
(11)
(12)
Hi-Z
SPN pin
Hi-Z
SVDD/2 Normal Output SVDD/2 Hi-Z
Example:
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency:44.1KHz
Digital Volume: 0dB
ALC: Enable
(1) Addr:05H, Data:27H
(2) Addr:02H, Data:20H
(3) Addr:03H, Data:08H
(4) Addr:06H, Data:3CH
(5) Addr:0BH, Data:28H
(6) Addr:07H, Data:40H
(7) Addr:0AH & 0DH, Data:91H
(8) Addr:00H, Data:74H
(9) Addr:02H, Data:A0H
Playback
(10) Addr:02H, Data:20H
(11) Addr:02H, Data:00H
(12) Addr:00H, Data:40H
Figure 43. Speaker-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4646 is PLL mode, DAC and Speaker-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC Æ SPK-Amp”: DACS bit = “0” Æ “1”
(3) SPK-Amp gain setting: SPKG1-0 bits = “00” Æ “01”
(4) Set up Timer Select for ALC (Addr: 06H)
(5) Set up REF value for ALC (Addr: 0BH)
(6) Set up LMTH0, RGAIN0, LMAT1-0 and ALC2 bits (Addr: 07H)
(7) Set up the output digital volume (Addr: 0AH and 0DH).
When OVOLC bit is “1” (default), OVL7-0 bits set the volume of both channels. After DAC is powered-up, the
digital volume changes from default value (0dB) to the register setting value by the soft transition. ALC/OVOL
are invalid to DAC when (PMADL bit = “1” or PMADR bit = “1”) and DAFIL bit = “0”.
(8) Power Up of DAC, MIN-Amp and Speaker-Amp: PMDAC = PMBP = PMSPK bits = “0” → “1”
The DAC outputs invalid voltage for 67/fs = 1.52ms@fs = 44.1kHz after powered-up, then it starts outputting
normal voltage.
(9) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”
“(9)” time depends on the time constant of external resistor and capacitor connected to MIN pin. If
Speaker-Amp output is enabled before input of MIN-Amp becomes stable, pop noise may occur.
e.g. R=20k, C=0.1μF: Recommended wait time is more than 5τ = 10ms.
(10) Enter the power-save-mode of Speaker-Amp: SPPSN bit = “1” → “0”
(11) Disable the path of “DAC Æ SPK-Amp”: DACS bit = “1” Æ “0”
(12) Power Down DAC, MIN-Amp and Speaker-Amp: PMDAC = PMBP = PMSPK bits = “1” → “0”
MS0630-E-00
- 72 -
2007/06