AK4646EZ Datasheet, PDF (25/78 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/SPK-AMP

[AK4646EZ]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4646 becomes EXT mode. Master clock can directly be inputted from MCKI pin, without
the internal PLL circuit operation. This mode is compatible with I/F of the normal audio CODEC. The clocks required to
operate this mode are MCKI (256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be
synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by
FS1-0 bits (Table 11).
Mode
0
1
2
3
Others
FS3-2 bits
FS1 bit FS0 bit
MCKI Input
Frequency
Sampling Frequency
Range
x
0
0
256fs
7.35kHz ∼ 48kHz (default)
x
0
1
1024fs
7.35kHz ∼ 13kHz
x
1
0
512fs
7.35kHz ∼ 26kHz
x
1
1
256fs
7.35kHz ∼ 48kHz
Others
N/A
N/A
(x: Don’t care, N/A: Not available)
Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through LOUT/ROUT pins at fs=8kHz is shown in Table 12.
MCKI
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
93dB
1024fs
93dB
Table 12. Relationship between MCKI and S/N of LOUT/ROUT pins
The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation
(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4646 may draw
excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. When the
external clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits
= “0”).
AK4646
MCKO
MCKI
BICK
LRCK
SDTO
SDTI
256fs, 512fs or 1024fs
DSP or μP
MCLK
≥ 32fs
BCLK
1fs
LRCK
SDTI
SDTO
Figure 16. EXT Slave Mode
MS0630-E-00
- 25 -
2007/06