AK4646EZ Datasheet, PDF (48/78 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/SPK-AMP

[AK4646EZ]
[Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)]
(2)
P M L O b it
(1 )
(3)
L O P S bit
(5)
(4)
(6)
L O U T , R O U T p in s
≥ 300 m s
N orm al O utput
≥ 300 m s
Figure 33. Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)
(1) Set LOPS bit = “1”. Stereo line output enters the power-save mode.
(2) Set PMLO bit = “1”. Stereo line output exits the power-down mode.
LOUT and ROUT pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1μF.
(3) Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits the power-save mode.
Stereo line output is enabled.
(4) Set LOPS bit = “1”. Stereo line output enters power-save mode.
(5) Set PMLO bit = “0”. Stereo line output enters power-down mode.
LOUT and ROUT pins fall down to AVSS. Fall time is 200ms (max 300ms) at C=1μF.
(6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode.
MS0630-E-00
- 48 -
2007/06