AK4646EZ Datasheet, PDF (52/78 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/SPK-AMP

[AK4646EZ]
■ Serial Control Interface
Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTIO). The data on this
interface consists of Read/Write, Register address (MSB first, 7bits) and Control data (MSB first, 8bits). Each bit is
clocked in on the rising edge (“↑”) of CCLK. It is available for writing data on the rising edge of CSN. When reading
operation, CDTIO pin has become an output mode at the falling edge of 8^th CCLK and outputs D7-D0. The output
finishes on the rising edge of CSN. The CDTIO is placed in a Hi-Z state except outputting data at read operation mode.
Clock speed of CCLK is 5MHz (max). The value of internal registers are initialized by PDN pin = “L”.
Note 40. It is available for reading the address 00H~11H. When reading the address 12H ∼ 4FH, the register values are
invalid.
CSN
CCLK _{“H” or “L”}
0 _{1 2 3 4 5 6 7 8 9 10 11 12 13 14 15}
“H” or “L”
CDTIO “H” or “L”
A6 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 “H” or “L”
R/W:
A6-A0:
D7-D0:
READ/WRITE (“1”: WRITE, “0”: READ)
Register Address
Control data (Input) at Write Command
Output data (Output) at Read Command
Figure 36. Serial Control I/F Timing
MS0630-E-00
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2007/06