AK4646EZ Datasheet, PDF (38/78 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/SPK-AMP

[AK4646EZ]
■ ALC Operation
The ALC (Automatic Level Control) is operated by ALC block when ALC bit is “1”. When both Lch and Rch of ADC are
powered-down or DAFIL bit is “1”, ALC circuit operates at playback path. When either Lch and Rch of ADC is
powered-up and DAFIL bit is “0”, ALC circuit operates at recording path.
Note 37. In this section, VOL means IVL and IVR for recording path, OVL and OVR for playback path.
Note 38. In this section, ALC bit means ALC1 bit for recording path, ALC2 bit for playback path.
Note 39. In this section, REF means IREF for recording path, OREF for playback path.
1. ALC Limiter Operation
During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 23), the VOL
value (same value for both L and R) is attenuated automatically by the amount defined by the ALC limiter ATT step
(Table 24). The VOL is then set to the same value for both channels.
When ZELMN bit = “0” (zero cross detection is enabled), the VOL value is changed by ALC limiter operation at the
individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing timeout
period of both ALC limiter and recovery operation (Table 25). In addition, when LFST bit = “1”, in the case of a output
level exceeding FS, it is changed in 1Step (L/R common) instantly (cycle: 1/fs). In the case of an output level does not
exceeding FS, it is zero crossing or VOL value is changed at the time of being zero crossing timeout.
When ZELMN bit = “1” (zero cross detection is disabled), VOL value is immediately (period: 1/fs) changed by ALC
limiter operation. Attenuation step is fixed to 1 step regardless as the setting of LMAT1-0 bits.
The attenuation operation is done continuously until the input signal level becomes ALC limiter detection level (Table 23)
or less. After completing the attenuation operation, unless ALC bit is changed to “0”, the operation repeats when the input
signal level exceeds LMTH1-0 bits.
LMTH1
0
0
1
1
LMTH0 ALC Limiter Detection Level ALC Recovery Waiting Counter Reset Level
0
ALC Output ≥ −2.5dBFS
−2.5dBFS > ALC Output ≥ −4.1dBFS
1
ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
0
ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
1
ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
Table 23. ALC Limiter Detection Level / Recovery Counter Reset Level
(default)
LMAT1
0
0
1
1
ALC1 Limiter ATT Step
LMAT0 _{ALC1 Output ALC1 Output ALC1 Output}
≥ LMTH
≥ FS
≥ FS + 6dB
0
1
1
1
1
2
2
2
0
2
4
4
1
1
2
4
Table 24. ALC Limiter ATT Step (x: Don’t care)
ALC1 Output
≥ FS + 12dB
1
(default)
2
8
8
ZTM1
0
0
1
1
ZTM0
0
1
0
1
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 25. ALC Zero Crossing Timeout Period
(default)
MS0630-E-00
- 38 -
2007/06