AK4646EZ Datasheet, PDF (15/78 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/SPK-AMP

■ Timing Diagram
MCKI
LRCK
MCKO
1/fCLK
VIH
VIL
tCLKH
tCLKL
1/fs
tLRCKH
tLRCKL
1/fMCK
50%DVDD
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tMCKL
50%DVDD
dMCK = tMCKL x fMCK x 100
Note 31. MCKO is not available at EXT Master mode.
Figure 2. Clock Timing (PLL / EXT Master mode)
[AK4646EZ]
LRCK
50%DVDD
BICK
tBLR
tDLR
tBCKL
tBSD
50%DVDD
SDTO
50%DVDD
SDTI
tSDS
tSDH
VIH
VIL
Figure 3. Audio Interface Timing (PLL/EXT Master mode)
MS0630-E-00
- 15 -
2007/06