AK4646EZ Datasheet, PDF (47/78 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/SPK-AMP

[AK4646EZ]
■ Stereo Line Output (LOUT/ROUT pins)
When DACL bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When
DACL bit is “0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10kΩ
(min.). When the PMLO bit = LOPS bit = “0”, the stereo line output enters power-down mode and the output is
pulled-down to AVSS by 100kΩ(typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at
power-up/down can be reduced by changing PMLO bit at LOPS bit = “1”. In this case, output signal line should be
pulled-down to AVSS by 20kΩ after AC coupled as Figure 32. Rise/Fall time is 300ms (max) at C=1μF. When PMLO bit
= “1” and LOPS bit = “0”, stereo line output is in normal operation.
LOVL bit set the gain of stereo line output.
DAC
“DACL”
“LOVL”
LOUT pin
ROUT pin
LOPS
0
1
Figure 31. Stereo Line Output
PMLO
Mode
LOUT/ROUT pin
0
Power-down
Pull-down to AVSS
1
Normal Operation
Normal Operation
0
Power-save
Fall down to AVSS
1
Power-save
Rise up to VCOM
Table 40. Stereo Line Output Mode Select
(default)
LOVL1-0 bits
Gain
00
0dB (default)
01
+2dB
10
+4dB
11
+6dB
Table 41. Stereo Line Output Volume Setting
LOUT 1μF
ROUT
220Ω
20kΩ
Figure 32. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit)
MS0630-E-00
- 47 -
2007/06