AK5366VR Datasheet, PDF (39/42 Pages) Asahi Kasei Microsystems – 24-Bit 48kHz ΔΣ ADC with Selector/PGA/ALC

ASAHI KASEI
[AK5366VR]
SYSTEM DESIGN
Figure 25 shows the system connection diagram. An evaluation board is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
• Master Mode, 3-wire control (I2C pin = “L”)
1µ
1µ
1µ
1µ
1µ
47k
47k
47k
47k
47k
48 47 46 45 44 43 42 41 40 39 38 37
1µ _47k
1µ _47k
1µ _47k
1µ _47k
1µ _47k
24k
4.7µ
1 LIN5
2 TEST1
3 LIN4
4 TEST2
5 LIN3
6 TEST3
7 LIN2
8 TEST4
9 LIN1
10 NC
11 LOPIN
12 LOUT
Top View
13 14 15 16 17 18 19 20 21 22
CSN/CAD1 36
CCLK/SCL 35
CDTI/SDA 34
SEL2 33
SEL1 32
SEL0 31
SMUTE 30
TVDD 29
PDN 28
MCLK 27
LRCK 26
BICK 25
23 24
4.7µ ^24k
0.1µ 0.1µ
0.1µ
10µ 2.2µ
10µ
10
0.1µ
Reset
DSP and uP
Analog Supply
4.75 ~ 5.25V
Digital Supply
3.0 ~ 5.25V
Note:
- AVSS and DVSS of the AK5366VR should be distributed separately from the ground of external digital
devices
(MPU, DSP etc.).
- When LOUT/ROUT drives a capacitive load, resistors should be added in series between LOUT/ROUT
and capacitive load.
- All digital input pins should not be left floating.
- M/S pin should be connected to AVDD or AVSS.
Figure 25. Typical Connection Diagram
MS0526-E-00
- 39 -
2006/07