AK5366VR Datasheet, PDF (35/42 Pages) Asahi Kasei Microsystems – 24-Bit 48kHz ΔΣ ADC with Selector/PGA/ALC

ASAHI KASEI
[AK5366VR]
Addr
03H
Register Name
Timer Select
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
LTM1 LTM0 ZTM1 ZTM0 WTM1 WTM0
RD
RD
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
1
0
1
1
WTM1-0: ALC Recovery waiting time (see Table 14)
A period of recovery operation when any limiter operation does not occur during the ALC operation.
WTM1
0
0
1
1
WTM0
0
1
0
1
ALC recovery operation waiting period
288/fs
1152/fs
2304/fs
4608/fs
Table 14. ALC recovery waiting time
@fs=48kHz
6ms
24ms
48ms
96ms
Default
ZTM1-0: Zero crossing timeout (see Table 15)
When the IPGA of each L/R channels perform zero crossing or timeout independently, the IPGA value is
changed by the µP WRITE operation, ALC recovery operation or ALC limiter operation (ZELMN bit = “0”).
ZTM1
0
0
1
1
ZTM0
0
1
0
1
Zero crossing timeout period
288/fs
1152/fs
2304/fs
4608/fs
Table 15. Zero crossing timeout
@fs=48kHz
6ms
24ms
48ms
96ms
Default
LTM1-0: ALC Limiter period (see Table 16)
When ZELMN bit = “1”, the IPGA value is changed immediately. When the IPGA value is changed
continuously, the change is done by the period set by the LTM1-0 bits.
LTM1
0
0
1
1
LTM0
0
1
0
1
ALC limiter operation period
3/fs
6/fs
12/fs
24/fs
Table 16. ALC limiter period
@fs=48kHz
63µs
125µs
250µs
500µs
Default
MS0526-E-00
- 35 -
2006/07