AK5366VR Datasheet, PDF (32/42 Pages) Asahi Kasei Microsystems – 24-Bit 48kHz ΔΣ ADC with Selector/PGA/ALC

ASAHI KASEI
[AK5366VR]
SDA
SCL
S
start condition
P
stop condition
Figure 22. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
SCL FROM
MASTER
S
START
CONDITION
not acknowledge
1
2
Figure 23. Acknowledge on the I²C-Bus
acknowledge
8
9
clock pulse for
acknowledgement
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 24. Bit Transfer on the I²C-Bus
MS0526-E-00
- 32 -
2006/07